Decimal Floating-Point IP Family

This intellectual property (IP) family presents new designs for decimal floating point (DFP) addition, multiplication, fused multiply-add, division, and square root. All the IP cores are using the IEEE 754-2008 Decimal Interchange format encoding, and most of them support both decimal64 (16 digits) and decimal128 (34 digits) formats. We areconstantly working on designing and implementing hardware IP cores for decimal floating-point arithmetic. We aims to promote the development of computer arithemtic with high standard, reliable and cost effective decimal arithmetic cores, which can be flexibly extended and verified for the technology industrial.

DFP and Decimal Integer Adder IP:
1. A 16-digit FXP decimal CLA adder in BCD encoding (based on [You06]) done
2. A Fully Redundant Decimal Adder (based on [Saeid09], [Kaivani09]) on-going
3. A decimal64/128 DFP adder/substracter (based on [Alvaro09], [Liang09], [Liang07]) on-going

DFP Multiplier IP:
1. A 16-digit FXP Decimal Combinational Multiplier (based on [Lang06]) done
2. A 16-digit FXP Decimal Sequential Multiplier (based on [Mark]) done
3. Improving the Speed for Decimal Multiplier (based on [Ghassem]) on-going
4. A decimal64/128 DFP Multiplier (based on [Mark]) on-going

DFP Divider IP:
1. A decimal64 Decimal Divider based on Newton-Raphson Iteration (based on [Liang]) done
2. A decimal64 Decimal Divider based on Non-Restore Algorithm (based on [Eric]) done
3. A decimal64/128 DFP Division/Square Root Unit Based on Digit-Recurrence SRT(based on [Lang], [Liang], [Hooman], [Alvaro] on-going

DFP Transcendental Arithmetic IP:
1. A decimal32 DFP Logarithmic Converter (based on [Chen]) done
2. A decimal32 DFP Antilogarithmic Converter (based on [Chen]) done
3. A FXP decimal-to-decimal Logarithmic Converter (based on [Chen]) done
4. A FXP decimal-to-decimal Antilogarithmic Converter (based on [Chen]) done
5. A decimal64 DFP Reciprocal Unit (based on [Chen] [Liang]) done
6. A decimal64 DFP Square Root Unit (based on [Liang]) done
7. A Cordic-based Architecture (based on [Avaro] [Sanchez]) on-going
8. A decimal FXP transcendental function evaluation platform on-going

Other Related Arithmetic IP:
1. A decimal floating-point Comparator (based on [Ivan]) on-going
2. A combined rounding/normalization unit for binary integer decimals (BID) (based on [Tsen], [Sonia]) done
3. A SIMD support architecture for DFP arithmetic (based on [Power6]) on-going