During My Ph.D, we have furthered several research projects in the field of DFP arithmetic. A series of decimal Fixed-Point (FXP) and DFP arithmetic IP cores have been designed and implemented to support the new decimal formats (decimal32, decimal64 and decimal128) defined in the IEEE 754-2008. The goal of my Ph.D research is to develop efficient algorithms, architectures, and VLSI circuit designs for DFP transcendental functions computation in order to obtain an improved understanding of potential costs and benefits of the current microprocessor support for the DFP transcendental arithmetic. The term decimal transcendental functions refers to the following DFP mathematical operations: logarithms (log10(DFP) or ln(FXP)), antilogarithms (10^DFP), exponential (e^FXP), reciprocal (DFP^−1), square root (DFP^1/2 ) and division (DFP1/DFP2) etc., where DFP presents anyone of the three DFP formats, and FXP presents the decimal significand in DFP formats, which are specified in the IEEE 754-2008 standard.
2. Collaborative Research Projects
3. Future Research Projects: (Refer to Research Statement)
Microelectronics promises a high component density and low power dissipation to embedded systems. Unfortunately such a component will always suffer from various error types that make the chip respond differently from its functional simulation. This is especially true for Cellular Neural Networks (CNN), which makes the determination of robust, low-precision parameters to guarantee small footprint and reliable operation an important design consideration. This thesis describes the digital word width effects in a CNN implementation that must be considered to achieve a small size for a reliable system. It discusses the automated design space exploration using a Field-Programmable Gate-Array (FPGA) implementation to perform an optimal CNN parameters selection.
2. Design and Implementation of a Reciprocal Unit based on Newton-Raphson Iteration (Started Nov 2004, IC Project and Verification ) Refer to Publication [C10]
This research presents the design and implementation of a reciprocal unit, in which the initial approximation of the reciprocal is obtained using a look-up table and a multiplication. How to create a look-up Table efficiently is described in detail, and the error analysis for the ROMs of different sizes is also given in this paper. The presented design utilizes a 2^7 ×16 bits ROM followed by two Newton-Raphson iterations. It takes 10 clock cycles to achieve the 52-bit accuracy approximation of the reciprocal of a double precision floating-point number. The proposed reciprocal unit is implemnted in the Xilinx FPGA and AMS 0.35-um CMOS process respectively. The functionality of the chip was successfully verified.
3. Developed an Accelerator for the Greatest Common Divisor (GCD) on FPGA (Started Jan 2005, Emmbedded System Course Project)
Proposed the hardware/software solution for Accelerator of the Greatest Common Divisor (GCD) of N-numbers problem. The development and testing was carried out using the Xilinx Embedded Development Kit and the MB1000 Virtex II evaluation board.
4. Design and Implementation of A Time Multiplexed FIR-filter in AMS 0.35-um CMOS Process (Started Jan 2005, DSP Course Project) Write RTL code, synthesis and post-synthesis simulation and Place & Route.
5. Developed a VGA controller on FPGA (Started Sept 2004, Introduction of VLSI Architecture Course project) Write HDL code , Simulate it with Modelsim and synthesize with Synplify Pro.